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rf pll frequency synthesizers adf4116/adf4117/adf4118 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2000C2007 analog devices, inc. all rights reserved. features adf4116: 550 mhz adf4117: 1.2 ghz adf4118: 3.0 ghz 2.7 v to 5.5 v power supply separate v p allows extended tuning voltage in 3 v systems y grade: ?40c to +125c dual-modulus prescaler adf4116: 8/9 adf4117/adf4118: 32/33 3-wire serial interface digital lock detect power-down mode fastlock mode applications base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless handsets (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment catv equipment general description the adf411x family of frequency synthesizers can be used to implement local oscillators (lo) in the upconversion and downconversion sections of wireless receivers and transmitters. they consist of a low noise digital phase frequency detector (pfd), a precision charge pump, a programmable reference divider, programmable a and b counters, and a dual-modulus prescaler (p/p + 1). the a (5-bit) and b (13-bit) counters, in conjunction with the dual-modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter) allows selectable ref in frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). all of the on-chip registers are controlled via a simple 3-wire interface. the devices operate with a power supply ranging from 2.7 v to 5.5 v and can be powered down when not in use. functional block diagram reference n = bp + a function latch prescaler p/p + 1 14-bit r counter 13-bit b counter 5-bit a counter 21-bit input register r counter latch a, b counter latch phase frequency detector charge pump m3 m2 m1 high z mux muxout cp fl o fl o switch 18 13 14 19 sd out sd out from function latch 5 dgnd agnd ce rf in b rf in a le data clk ref in cpgnd v p dv dd av dd av dd lock detect adf4116/adf4117/adf4118 load load 00392-001 figure 1.
adf4116/adf4117/adf4118 rev. d | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 circuit description......................................................................... 12 reference input section............................................................. 12 rf input stage............................................................................. 12 prescaler (p/p + 1)...................................................................... 12 a counter and b counter ......................................................... 12 r counter .................................................................................... 12 phase frequency detector (pfd) and charge pump............ 13 muxout and lock detect...................................................... 13 input shift register..................................................................... 13 latch summaries ........................................................................ 14 latch maps .................................................................................. 15 function latch................................................................................ 19 counter reset ............................................................................. 19 power-down ............................................................................... 19 muxout control..................................................................... 19 phase detector polarity ............................................................. 19 charge pump three-state......................................................... 19 fastlock enable bit ..................................................................... 19 fastlock mode bit....................................................................... 19 timer counter control ............................................................. 19 initialization latch ..................................................................... 20 device programming after initial power-up ........................ 20 applications information .............................................................. 21 local oscillator for the gsm base station transmitter........ 21 shutdown circuit ....................................................................... 21 direct conversion modulator .................................................. 21 interfacing ................................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 4/07rev. c to rev. d changes to ref in characteristics section..................................... 3 changes to table 4............................................................................ 7 changes to figure 35...................................................................... 22 changes to ordering guide .......................................................... 25 11/05rev. b to rev. c changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to table 3............................................................................ 6 changes to table 4............................................................................ 7 changed osc 3b1-13m0 to fox801bh-130 ............................ 21 changes to ordering guide .......................................................... 25 9/04rev. a to rev. b changes to specifications.................................................................3 changes to ordering guide .......................................................... 25 3/01rev. 0 to rev. a 4/00rev. 0: initial version
adf4116/adf4117/adf4118 rev. d | page 3 of 28 specifications av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v; agnd = dgnd = cpgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 . table 1. parameter b version 1 y version 2 unit test conditions/comments rf characteristics rf input sensitivity ?15 to 0 ?10 to 0 dbm min to max av dd = 3 v ?10 to 0 ?10 to 0 dbm min to max av dd = 5 v rf input frequency adf4116 80 to 550 mhz min to max see figure 26 for input circuit 45 to 550 mhz min to max input level = ?8 dbm; for lower frequencies, ensure slew rate (sr) > 36 v/s adf4117 0.1 to 1.2 ghz min to max adf4118 0.1 to 3.0 0.1 to 3.0 ghz min to max input level = ?10 dbm 0.2 to 3.0 ghz min to max input level = ?15 dbm maximum allowable prescaler output frequency 3 165 200 165 200 mhz max mhz max av dd , dv dd = 3 v av dd , dv dd = 5 v ref in characteristics reference input frequency 5 to 100 5 to 100 mhz min to max for f < 5 mhz, ensure sr > 100 v/s reference input sensitivity 4 , 5 0.4 to av dd 0.4 to av dd v p-p min to max av dd = 3.3 v, biased at av dd /2 0.7 to av dd 0.7 to av dd v p-p min to max for f 10 mhz, av dd = 5 v, biased at av dd /2 ref in input capacitance 10 10 pf max ref in input current 100 100 a max phase detector frequency 5 55 55 mhz max charge pump i cp sink/source high value 1 1 ma typ low value 250 250 a typ absolute accuracy 2.5 2.5 % typ i cp three-state leakage current 3 25 na max 1 16 na typ sink and source current matching 3 3 % typ 0.5 v v cp v p ? 0.5 i cp vs. v cp 2 2 % typ 0.5 v v cp v p ? 0.5 i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max reference input current 100 100 a max logic outputs v oh , output high voltage dv dd ? 0.4 dv dd ? 0.4 v min i oh = 500 a v ol , output low voltage 0.4 0.4 v max i ol = 500 a
adf4116/adf4117/adf4118 rev. d | page 4 of 28 parameter b version 1 y version 2 unit test conditions/comments power supplies av dd 2.7 to 5.5 2.7 to 5.5 v min to v max dv dd av dd av dd v p av dd to 6.0 av dd to 6.0 v min to v max av dd v p 6.0 v i dd (ai dd + di dd ) 6 adf4116 5.5 ma max 4.5 ma typical adf4117 5.5 ma max 4.5 ma typical adf4118 7.5 7.5 ma max 6.5 ma typical i p 0.4 0.4 ma max t a = 25c low-power sleep mode 1 1 a typ noise characteristics adf4118 normalized phase noise floor 7 ?213 ?213 dbc/hz typ phase noise performance 8 @ vco output adf4116 540 mhz output 9 ?89 ?89 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4117 900 mhz output 10 ?87 ?87 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4118 900 mhz output 10 ?90 ?90 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4117 836 mhz output 11 ?78 ?78 dbc/hz typ @ 300 hz offset and 30 khz pfd frequency adf4118 1750 mhz output 12 ?85 ?85 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4118 1750 mhz output 13 ?65 ?65 dbc/hz typ @ 200 hz offset and 10 khz pfd frequency adf4118 1960 mhz output 14 ?84 ?84 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency spurious signals adf4116 540 mhz output 10 ?88/?99 ?88/?99 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4117 900 mhz output 10 ?90/?104 ?90/?104 dbc typ @ 200 kh z/400 khz and 200 khz pfd frequency adf4118 900 mhz output 10 ?91/?100 ?91/?100 dbc typ @ 200 kh z/400 khz and 200 khz pfd frequency adf4117 836 mhz output 11 ?80/?84 ?80/?84 dbc typ @ 30 khz/60 khz and 30 khz pfd frequency adf4118 1750 mhz output 12 ?88/?90 ?88/?90 dbc typ @ 200 kh z/400 khz and 200 khz pfd frequency adf4118 1750 mhz output 13 ?65/?73 ?65/?73 dbc typ @ 10 kh z/20 khz and 10 khz pfd frequency adf4118 1960 mhz output 14 ?80/?86 ?80/?86 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency 1 operating temperature range for the b version is ?40c to +85c. 2 operating temperature range for the y version is ?40c to +125c. 3 this is the maximum operating fr equency of the cmos counters. 4 ac coupling ensures av dd /2 bias. see figure 35 for typical circuit. 5 guaranteed by design. 6 t a = 25c; av dd = dv dd = 3 v; rf in for adf4116 = 540 mhz; rf in for adf4117, adf4118 = 900 mhz. 7 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco, pn tot , and subtracting 20logn (where n is the n divider value) and 10logf pfd : pn synth = pn tot C 10logf pfd C 20logn. 8 the phase noise is measured with the eval-adf411xeb and the hp8562e spectrum analyzer. the spec trum analyzer provides the ref in for the synthesizer (f refout = 10 mhz @ 0 dbm). 9 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 540 mhz; n = 2700; loop bandwidth = 20 khz. 10 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop bandwidth = 20 khz. 11 f refin = 10 mhz; f pfd = 30 khz; offset frequency = 300 hz; f rf = 836 mhz; n = 27867; loop bandwidth = 3 khz. 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1750 mhz; n = 8750; loop bandwidth = 20 khz. 13 f refin = 10 mhz; f pfd = 10 khz; offset frequency = 200 hz; f rf = 1750 mhz; n = 175000; loop bandwidth = 1 khz. 14 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1960 mhz; n = 9800; loop bandwidth = 20 khz.
adf4116/adf4117/adf4118 rev. d | page 5 of 28 timing characteristics av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p < 6.0 v; agnd = dgnd = cpgnd = 0 v; t a = t min to t max , unless otherwise noted. guaranteed by design, but not production tested. table 2. parameter limit at t min to t max (b, y version) unit test conditions/comments t 1 10 ns min data to clk setup time t 2 10 ns min data to clk hold time t 3 25 ns min clk high duration t 4 25 ns min clk low duration t 5 10 ns min clk to le setup time t 6 20 ns min le pulse width clk dat a le le db20 (msb) db19 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 5 t 2 t 4 t 6 t 1 t 3 00392-002 figure 2. timing diagram
adf4116/adf4117/adf4118 rev. d | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +7 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd 1 ?0.3 v to +7 v v p to av dd ?0.3 v to +5.5 v digital i/o voltage to gnd 1 ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd 1 ?0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd 1 ?0.3 v to v dd + 0.3 v rf in a to rf in b 320 mv operating temperature range industrial (b version) ?40c to +85c extended (y version) ?40c to +125c storage temperature range ?65c to +150c maximum junction temperature 150c tssop ja thermal impedance 112c/w reflow soldering peak temperature 260c time at peak temperature 40 sec transistor count cmos 6425 bipolar 303 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
adf4116/adf4117/adf4118 rev. d | page 7 of 28 pin configuration and function descriptions 1 2 3 4 5 6 7 8 adf4116/ adf4117/ adf4118 16 15 14 13 12 11 10 9 cp cpgnd agnd av dd rf in a rf in b fl o dv dd muxout le ce ref in dgnd clk data v p top view (not to scale) 00392-003 figure 3. pin configuration table 4. pin function descriptions pin o. nemonic description 1 fl o fast lock switch output. this can be used to switch an external resistor to change the loop filter bandwidth and speed up locking the pll. 2 cp charge pump output. when enabled, this provides the i cp to the external loop filter, which in turn drives the external vco. 3 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 agnd analog ground. this is the ground return path for the prescaler. 5 rf in b complementary input to the rf prescaler. this point sh ould be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 26 . 6 rf in a input to the rf prescaler. this small si gnal input is ac-coupled from the vco. 7 av dd analog power supply. this can range from 2.7 v to 5.5 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must have the same value as dv dd . 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k. see figure 25 . the oscillator input can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 9 dgnd digital ground. 10 ce chip enable. a logic low on this pin powers down the d evice and puts the charge pump output into three-state mode. taking the pin high powers up the device de pending on the status of the power-down bit f2. 11 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 21-bit shift register on the clk rising edge. th is input is a high impedance cmos input. 12 data serial data input. the serial data is loaded msb first with the two lsbs as the control bits. this input is a high impedance cmos input. 13 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 dv dd digital power supply. this can range from 2.7 v to 5.5 v. deco upling capacitors to the digital ground plane (1 f, 1 nf) should be placed as close as possible to this pin. for best performance, the 1 f capacitor should be placed within 2 mm of the pin. the placing of the 1 nf capacitor is less critical, but should still be within 5 mm of the pin. dv dd must have the same value as av dd . 16 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, this supply can be set to 6 v and used to drive a vco with a tuning range of up to 6 v.
adf4116/adf4117/adf4118 rev. d | page 8 of 28 typical performance characteristics freq mags11 angs11 0.95 0.92087 ?36.961 1.00 0.93788 ?39.343 1.05 0.9512 ?40.134 1.10 0.93458 ?43.747 1.15 0.94782 ?44.393 1.20 0.96875 ?46.937 1.25 0.92216 ?49.6 1.30 0.93755 ?51.884 1.35 0.96178 ?51.21 1.40 0.94354 ?53.55 1.45 0.95189 ?56.786 1.50 0.97647 ?58.781 1.55 0.98619 ?60.545 1.60 0.95459 ?61.43 1.65 0.97945 ?61.241 1.70 0.98864 ?64.051 1.75 0.97399 ?66.19 1.80 0.97216 ?63.775 freq mags11 angs11 0.05 0.89207 ?2.0571 0.10 0.8886 ?4.4427 0.15 0.89022 ?6.3212 0.20 0.96323 ?2.1393 0.25 0.90566 ?12.13 0.30 0.90307 ?13.52 0.35 0.89318 ?15.746 0.40 0.89806 ?18.056 0.45 0.89565 ?19.693 0.50 0.88538 ?22.246 0.55 0.89699 ?24.336 0.60 0.89927 ?25.948 0.65 0.87797 ?28.457 0.70 0.90765 ?29.735 0.75 0.88526 ?31.879 0.80 0.81267 ?32.681 0.85 0.90357 ?31.522 0.90 0.92954 ?34.222 param-type data-format keyword impedance- ohms freq- unit ghz s ma r 50 00392-004 figure 4. s-parameter data for the adf4118 rf input (up to 1.8 ghz) rf input frequency (ghz) 04 . 0 0.5 1.5 2.0 2.5 3.0 3.5 ?35 rf input power (dbm) 0 ?15 ?20 ?25 ?30 ?5 ?10 1.0 v dd = 3v v p = 3v t a = ?40c ?40 ?45 t a = +25c t a = +85c 00392-005 figure 5. input sensitivity (adf4118) ?2khz ?1khz 900mhz 1khz 2khz reference level = ?4.2dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?90.2dbc/hz v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 22 00392-006 figure 6. adf4118 phase noise (900 mhz, 200 khz, 20 khz) r l = ?40dbc/hz 10db/division rms noise = 0.64 100hz frequency offset from 900mhz carrier 1mhz phase noise (dbc/hz) ?40 ?80 ?100 ?50 ?70 ?60 ?90 ?110 ?120 ?130 ?140 0.64 rms 00392-007 figure 7. adf4118 integrated phase noise (900 mhz, 200 khz, 35 khz, typical lock time: 200 s) r l = ?40dbc/hz 10db/division rms noise = 0.575 100hz frequency offset from 900mhz carrier 1mh phase noise (dbc/hz) ?40 ?70 ?80 ?90 ?100 ?50 ?60 ?110 ?120 ?130 ?140 0.575 rms 00392-008 z figure 8. adf4118 integrated phase noise (900 mhz, 200 khz, 20 khz, typical lock time: 400 s) ?400khz ?200khz 900mhz 200khz 400khz reference level = ?3.8dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?91.5dbc v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 4 00392-009 figure 9. adf4118 reference spurs (900 mhz, 200 khz, 20 khz)
adf4116/adf4117/adf4118 rev. d | page 9 of 28 ?400khz ?200khz 900mhz 200khz 400khz reference level = ?4.2dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?90.67dbc v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 200khz loop bandwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 10 00392-010 figure 10. adf4118 reference spurs (900 mhz, 200 khz, 35 khz) ?400khz ?200khz 1750mhz 200khz 400khz reference level = ?7.0dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?71.5dbc/hz v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 30khz loop bandwidth = 5khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 25 00392-011 figure 11. adf4118 phase noise (1750 mhz, 30 khz, 3 khz) r l = ?40dbc/hz 10db/division rms noise = 2.0 100hz frequency offset from 1.75ghz carrier 1mhz phase noise (dbc/hz) ?40 ?70 ?80 ?90 ?100 ?50 ?60 ?110 ?120 ?130 ?140 2.0 rms 00392-012 figure 12. adf4118 integrated phase noise (1750 mhz, 30 khz, 3 khz) ?60khz ?30khz 1750mhz 30khz 60khz reference level = ?7.0dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?72.3dbc v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 5khz res. bandwidth = 300hz video bandwidth = 300hz sweep = 4.2ms averages = 20 00392-013 figure 13. adf4118 reference spurs (1750 mhz, 30 khz, 3 khz) ?2khz ?1khz 2800mhz 1khz 2khz vv dd = 3v, v p = 5v i cp = 1ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 26 reference level = ?10.3dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 ?85.2dbc/hz 00392-014 figure 14. adf4118 phase noise (2800 mhz, 1 mhz, 100 khz) 10db/division r l = ?40dbc/hz rms noise = 1.552 100hz frequency offset from 2.8ghz carrier 1mhz phase noise (dbc/hz) ?40 ?70 ?80 ?90 ?100 ?50 ?60 ?110 ?120 ?130 ?140 1.55 rms 00392-015 figure 15. adf4118 integrated phase noise (2800 mhz, 1 mhz, 100 khz)
adf4116/adf4117/adf4118 rev. d | page 10 of 28 ?2mhz ?1mhz 1mhz 2mhz v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 3khz video bandwidth = 3khz sweep = 1.4 seconds averages = 4 reference level = ?9.3dbm output power (db) 0 ?50 ?70 ?80 ?90 ?10 ?30 ?60 ?40 ?20 ?100 2800mhz ?77.3dbc 00392-016 figure 16. adf4118 reference spurs (2800 mhz, 1 mhz, 100 khz) phase detector frequency (khz) 1 10000 100 1000 ?175 phase noise (dbc/hz) ?145 ?150 ?160 ?170 ? 130 ?135 10 ?165 ?155 ?140 v dd = 3v v p = 5v 00392-017 figure 17. adf4118 phase noise (referred to cp output) vs. pfd frequency ?40 phase noise (dbc/hz) ? 60 ?80 ?90 ?70 ?100 temperature (c) ?20 0 20 40 60 80 100 v dd = 3v v p = 5v 00392-018 figure 18. adf4118 phase noise vs. temperature (900 mhz, 200 khz, 20 khz) ?40 first reference spur (dbc) ? 60 ?80 ?90 ?70 ?100 temperature (c) ?20 0 20 40 60 80 100 v dd = 3v v p = 5v 00392-019 figure 19. adf4118 reference spurs vs. temperature (900 mhz, 200 khz, 20 khz) 0 first reference spur (dbc) 5 ?95 ?105 tuning voltage 1 v dd = 3v v p = 5v 234 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 00392-020 figure 20. adf4118 reference spurs (200 khz) vs. v tune (900 mhz, 200 khz, 20 khz) phase noise (dbc/hz) ? 60 ?80 ?90 ?70 temperature (c) 02 04 06 08 0 1 0 0 v dd = 3v v p = 5v 00392-021 figure 21. adf4118 phase noise vs. temperature (836 mhz, 30 khz, 3 khz)
adf4116/adf4117/adf4118 rev. d | page 11 of 28 first reference spur (dbc) ? 60 ?80 ?90 ?70 temperature (c) 0 20 40 60 80 100 v dd = 3v v p = 5v ?100 00392-022 figure 22. adf4118 reference spurs vs. temperature (836 mhz, 30 khz, 3 khz) 0 di dd (ma) 0 prescaler output frequency (mhz) 50 100 150 200 0.5 1.0 1.5 2.0 2.5 3.0 00392-023 figure 23. di dd vs. prescaler output frequency v cp (v) 01.0 i cp (ma) ?1.2 ?0.8 ?1.0 0.5 1.5 2.0 2.5 3.0 3.5 4.5 5.0 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 v p = 5v i cp setting: 1ma 4.0 00392-024 figure 24. charge pump output characteristics
adf4116/adf4117/adf4118 rev. d | page 12 of 28 circuit description reference input section the reference input stage is shown in figure 25 . sw1 and sw2 are normally closed switches; sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control buffer 00392-025 figure 25. reference input stage rf input stage the rf input stage is shown in figure 26 . it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the prescaler. av dd agnd 500 ? 500 ? 1.6v bias generator rf in a rf in b 00392-026 figure 26. rf input stage prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a counter and b counter, enables the large division ratio, n, to be realized (n = pb + a). the dual-modulus prescaler takes the cml clock from the rf input stage and divides it down to a manageable frequency for the cmos a counter and cmos b counter. the prescaler is programmable. it can be set in software to 8/9 for the adf4116 and to 32/33 for the adf4117 and adf4118. it is based on a synchronous 4/5 core. a counter and b counter the a cmos counter and b cmos counter combine with the dual-modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 200 mhz or less. pulse swallow function the a counter and b counter, in conjunction with the dual- modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: ( ) [ ] rfabpf refin vco / + = where: f vco is the output frequency of external voltage controlled oscillator (vco). p is the preset modulus of dual-modulus prescaler. b is the preset divide ratio of binary 13-bit counter (3 to 8191). a is the preset divide ratio of binary 5-bit swallow counter (0 to 31). f refin is the output frequency of the external reference frequency oscillator. r is the preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383). r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. 13-bit b counter 5-bit a counter prescaler p/p + 1 from rf input stage modulus control n = bp + a load load to pfd 00392-027 figure 27. a counter and b counter
adf4116/adf4117/adf4118 rev. d | page 13 of 28 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 28 is a simplified schematic of the pfd. the pfd includes a fixed delay element that sets the width of the antibacklash pulse. this is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. delay u3 clr1 q1 d1 cp down up hi u1 clr2 q2 d2 u2 hi n divider r divider v p charge pump cpgnd r divider cp output n divider 00392-028 figure 28. pfd simplified schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf411x family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. figure 33 shows the full truth table. figure 29 shows the muxout section in block diagram form. control mux dv dd muxout dgnd a nalog lock detect digital lock detect r counter output n counter output sdout 00392-029 figure 29. muxout circuit lock detect muxout can be programmed for both digital lock detect and analog lock detect. digital lock detect is active high. it is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. it stays set high until a phase error greater than 25 ns is detected on any subsequent pd cycle. the n channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 k nominal. when lock is detected, it is high with narrow low going pulses. input shift register the adf411x family digital section includes a 21-bit input shift register, a 14-bit r counter, and an 18-bit n counter, comprising a 5-bit a counter and a 13-bit b counter. data is clocked into the 21-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram in figure 2 . the truth table for these bits is shown in figure 34 . table 5 summarizes how the latches are programmed. table 5. programming data latches control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch 1 1 initialization latch
adf4116/adf4117/adf4118 rev. d | page 14 of 28 latch summaries lock detect precision test mode bits db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 ldp t4 t3 t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits db20 db19 db18 db17 db16 db1 5 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 g1 b13 b12 b11 b10 b9 b8 b7 b6 b5 b3 b2 b1 a5 a4 a3 a2 a1 c2 (0) c1 (1) b4 control bits 13-bit b counter 5-bit a counter cp gain db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) control bits muxout control power- down 2 power- down 1 phase detector polarity fastlock enable cp three- state fastlock mode timer counter control db20 db19 db18 db17 db16 db1 5 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 pd2 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) control bits muxout control power- down 2 power- down 1 counter reset counter reset fastlock enable cp three- state fastlock mode timer counter control reference counter l a tch ab counter latch function latch initialization latch reserved reserved pd2 x db20 x reserved xxx reserved reserved x x reserved xxx phase detector polarity 00392-030 figure 30. adf411x family latch summary
adf4116/adf4117/adf4118 rev. d | page 15 of 28 latch maps r14 0 0 0 0 ? ? ? 1 1 1 1 r13 0 0 0 0 ? ? ? 1 1 1 1 r12 0 0 0 0 ? ? ? 1 1 1 1 r3 r2 r1 divide ratio ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? 0 0 0 1 ? ? ? 1 1 1 1 0 1 1 0 ? ? ? 0 0 1 1 1 0 1 0 ? ? ? 0 1 0 1 1 2 3 4 ? ? ? 163 80 163 81 163 82 163 83 test mode bits should be set to 0000 for normal operation operation ldp 3 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 5 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 0 1 lock detect precision test mode bits db20 db19 db18 db17 db16 db15 db14 db13 db1 2 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 ldp t4 t3 t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits 00392-031 figure 31. reference counter latch map
adf4116/adf4117/adf4118 rev. d | page 16 of 28 current settings ldp 250a 0 1 a5 x x ? ? x x a4 x x ? ? x x a3 0 0 ? ? 1 1 a2 0 0 ? ? 1 1 a1 0 1 ? ? 0 1 a counter divide ratio 0 1 ? ? 6 7 b13 0 0 0 0 ? ? ? 1 1 1 1 b12 0 0 0 0 ? ? ? 1 1 1 1 b11 0 0 0 0 ? ? ? 1 1 1 1 b3 b2 b1 b counter divide ratio ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? 0 0 0 1 ? ? ? 1 1 1 1 0 1 1 0 ? ? ? 0 0 1 1 1 0 1 0 ? ? ? 0 1 0 1 not allowed not allowed 3 4 ? ? ? 8188 8189 8190 8191 adf4116 a5 0 0 0 ? ? 1 1 1 a4 0 0 0 ? ? 1 1 1 a3 0 0 0 ? ? 1 1 1 a2 0 0 1 ? ? 0 1 1 a1 0 1 0 ? ? 1 0 1 a counter divide ratio 0 1 2 ? ? 29 30 31 adf4117/adf4118 1ma n = bp + a, p is prescaler value. b must be greater than or equal to a. for continuously adjacent values of n x f ref , n min is (p 2 ? p). db20 db19 db18 db17 db16 db15 db14 db13 db1 2 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 g1 b13 b12 b11 b10 b9 b8 b7 b6 b5 b3 b2 b1 a5 a4 a3 a2 a1 c2 (0) c1 (1) b4 control bits 13-bit b counter 5-bit a counter cp gain 00392-032 figure 32. a counter/b counter latch map
adf4116/adf4117/adf4118 rev. d | page 17 of 28 m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output av dd r divider output analog lock detect (n channel open drain) serial data output (inverse polarity of serial data input) dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode x x 0 1 x 0 1 1 f6 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 asynchronous power-down normal operation asynchronous power-down synchronous power-down db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) control bits muxout control power- down 2 power- down 1 fastlock enable cp three- state fastlock mode timer counter control reserved reserved pd2 x db20 x reserved xxx phase detector polarity phase detector polarity 00392-033 counter reset figure 33. function latch map
adf4116/adf4117/adf4118 rev. d | page 18 of 28 m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output av dd r divider output analog lock detect (n channel open drain) serial data output (inverse polarity of serial data input) dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f6 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 db20 db19 db18 db17 db16 db1 5 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 pd2 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) control bits muxout control power- down 2 power- down 1 fastlock enable cp three- state fastlock mode timer counter control reserved reserved x x reserved xxx phase detector polarity phase detector polarity 00392-034 counter reset figure 34. initialization latch map
adf4116/adf4117/adf4118 rev. d | page 19 of 28 function latch with c2 and c1 set to 1 and 0, respectively, the on-chip function latch is programmed. figure 33 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this bit is set to 1, the r counter, a counter, and b counter are reset. for normal operation, this bit should be set to 0. on power-up, the f1 bit needs to be disabled, for the n counter to resume counting in close alignment with the r counter. (the maximum error is one prescaler cycle.) power-down db3 (pd1) and db19 (pd2) on the adf411x family provide programmable power-down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2 and pd1. in programmed asynchronous power-down, the device powers down immediately after latching a 1 into the pd1 bit, with the condition that pd2 is loaded with a 0. in programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. once power-down is enabled by writing a 1 into the pd1 bit (on condition that a 1 is also loaded to pd2), the device goes into power-down after the first successive charge pump event. when a power-down is activated (either synchronous or asynchronous mode including ce pin-activated power-down), the following events occur: ? all active dc current paths are removed. ? the r counter, n counter, and timeout counter are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital clock detect circuitry is reset. ? the rf in input is debiased. ? the oscillator input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by db6 (m3), db5 (m2), and db4 (m1) on the adf411x family. figure 33 shows the truth table. phase detector polarity db7 (f2) of the function latch sets the phase detector polarity. when the vco characteristics are positive, db7 should be set to 1. when they are negative, it should be set to 0. charge pump three-state the db8 (f3) bit puts the charge pump into three-state mode when programmed to 1. it should be set to 0 for normal operation. fastlock enable bit db9 (f4) of the function latch is the fastlock enable bit. fastlock is enabled only when db9 is set to 1. fastlock mode bit db11 (f6) of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected. if fastlock is not enabled (db9 = 0), db11 (adf4116) determines the state of the fl o output. fl o state is the same as that programmed to db11. fastlock mode 1 in the adf411x family, the output level of fl o is programmed to a low state, and the charge pump current is switched to the high value (1 ma). fl o is used to switch a resistor in the loop filter and to ensure stability while in fastlock by altering the loop bandwidth. the device enters fastlock by having a 1 written to the cp gain bit in the n register. the device exits fastlock by having a 0 written to the cp gain bit in the n register. fastlock mode 2 in the adf411x family, the output level of fl o is programmed to a low state, and the charge pump current is switched to the high value (1 ma). fl o is used to switch a resistor in the loop filter and to ensure stability while in fastlock by altering the loop bandwidth. the device enters fastlock by having a 1 written to the cp gain bit in the n register. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 to tc1, the cp gain bit in the n register is automatically reset to 0, and the device reverts to normal mode instead of fastlock. timer counter control in the adf411x family, the user has the option of switching between two charge pump current values to speed up locking to a new frequency. when using the fastlock feature with the adf411x family, the following should be noted: ? the user must make sure that fastlock is enabled. set db9 to 1. the user must also choose which fastlock mode to use.
adf4116/adf4117/adf4118 rev. d | page 20 of 28 ? fastlock mode 2 uses the values in the timer counter to determine the timeout period before reverting to normal mode operation after fastlock. fastlock mode 2 is chosen by setting db11 to 1. ? the user must also decide how long to keep the high current (1 ma) active before reverting to low current (250 a). this is controlled by the timer counter control bits, db14 to db11 (tc4 to tc1), in the function latch. the truth table is given in figure 33 . ? to program a new output frequency, program the a counter and b counter latch with new values for a and b. at the same time, set the cp gain bit to a 1, which sets the charge pump to 1 ma for a period of time determined by tc4 to tc1. when this time is up, the charge pump current reverts to 250 a. at the same time, the cp gain bit in the a counter and b counter latch is reset to 0 and is ready for the next time that the user wants to change the frequency. initialization latch when c2 and c1 are both set to 1, the initialization latch is programmed. this is essentially the same as the function latch that is programmed when c2, c1 = 1, 0. however, when the initialization latch is programmed, an additional internal reset pulse is applied to the r counter and n counter. this pulse ensures that the n counter is at a load point when the n counter data is latched and that the device begins counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; pd2 bit is low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. when the first n counter data is latched after initialization, the internal reset pulse is again activated. however, successive n counter loads do not trigger the internal reset pulse. device programming after initial power-up after initial power-up, the device can be programmed by the initialization latch method, the ce pin method, or the counter reset method. initialization latch method 1. apply v dd . 2. program the initialization latch (11 in 2 lsbs of input word). make sure that f1 bit is programmed to 0. 3. do an r load (00 in 2 lsbs). 4. do an n load (01 in 2 lsbs). when the initialization latch is loaded, the following occurs: ? the function latch contents are loaded. ? an internal pulse resets the r, n, and timeout counters to load state conditions and also three-states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. ? latching the first n counter data after the initialization word activates the same internal reset pulse. successive n loads do not trigger the internal reset pulse unless there is another initialization. ce pin method 1. apply v dd . 2. bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. 3. program the function latch (10). 4. program the r counter latch (00). 5. program the n counter latch (01). 6. bring ce high to take the device out of power-down. the r counter and n counter resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach a steady state. ce can be used to power up and power down the device to check for channel activity. the input register does not need to be repro- grammed each time the device is disabled and enabled, as long as it is programmed at least once after v cc is initially applied. counter reset method 1. apply v dd . 2. do a function latch load (10 in 2 lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. do an r counter load (00 in 2 lsbs). 4. do an n counter load (01 in 2 lsbs). 5. do a function latch load (10 in 2 lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initiali- zation method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but it does not trigger synchro- nous power-down. the counter reset method requires an extra function latch load compared to the initialization latch method.
adf4116/adf4117/adf4118 rev. d | page 21 of 28 applications information local oscillator for the gsm base station transmitter figure 35 shows the adf4117/adf4118 being used with a vco to produce the lo for a gsm base station transmitter. the reference input signal is applied to the circuit at f refin and, in this case, is terminated in 50 . a typical gsm system has a 13 mhz tcxo driving the reference input without a 50 termination. to have a channel spacing of 200 khz (the gsm standard), the reference input must be divided by 65, using the on-chip reference divider of the adf4117/adf1118. the charge pump output of the adf4117/adf1118 (pin 2) drives the loop filter. in calculating the loop filter component values, a number of items need to be considered. in this example, the loop filter was designed so that the overall phase margin for the system is 45. other pll system specifications include: k d = 1 ma k v = 12 mhz/v loop bandwidth = 20 khz f ref = 200 khz n = 4500 extra reference spur attenuation = 10 db all of these specifications are needed and are used to produce the loop filter component values shown in figure 36 . the loop filter output drives the vco, which, in turn, is fed back to the rf input of the pll synthesizer; it also drives the rf output terminal. a t-circuit configuration provides 50 matching between the vco output, the rf output, and the rf in terminal of the synthesizer. in a pll system, it is important to know when the system is in locked mode. in figure 35 , this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be programmed to monitor various internal signals in the synthesizer. one of these is the ld or lock-detect signal. shutdown circuit the attached circuit in figure 36 shows how to shut down both the adf411x family and the accompanying vco. the adg702 switch goes open-circuit when a logic 1 is applied to the in input. the low cost switch is available in both sot-23 and msop packages. direct conversion modulator in some applications, a direct conversion architecture can be used in base station transmitters. figure 37 shows the combination available from analog devices, inc. to implement this solution. the circuit diagram shows the ad9761 being used with the ad8346. the use of dual integrated dacs, such as the ad9761 with specified 0.02 db and 0.004 db gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator is implemented by using the adf4117/ adf4118. in this case, the fox801bh-130 provides the stable 13 mhz reference frequency. the system is designed for 200 khz channel spacing and an output center frequency of 1960 mhz. the target application is a wcdma base station transmitter. typical phase noise performance from this lo is ?85 dbc/hz at a 1 khz offset. the lo port of the ad8346 is driven in single-ended fashion. loin is ac-coupled to ground with the 100 pf capacitor, and loip is driven through the ac- coupling capacitor from a 50 source. an lo drive level between ?6 dbm and ?12 dbm is required. the circuit in figure 37 gives a typical level of ?8 dbm. the rf output is designed to drive a 50 load, but it must be ac-coupled as shown in figure 37 . if the i and q inputs are driven in quadrature by 2 v p-p signals, the resulting output power is approximately ?10 dbm.
adf4116/adf4117/adf4118 rev. d | page 22 of 28 vco190-902t v cc 18 ? 100pf 100pf 18 ? 18 ? rf out v dd v p av dd dv dd adf4117/ adf4118 v p 0.15nf 620pf 3.3k ? 71516 2 14 6 5 8 f refin 1000pf 1000pf 51 ? * *to be used when generator source impedance is 50 ? . muxout lock detect 51 ? ** 100pf 34 9 100pf cpgnd agnd dgnd rf in a rf in b ce clk data le spi-compatible serial bus decoupling capacitors on av dd ,dv dd , and v p of the adf4117/adf4118 and on v cc of the vco190-920t have been omitted from the diagram for clarity. fl o cp 10k ? 1.5nf 27k ? ref in 1 00392-035 **optional matching resistor depending on rf out frequency. figure 35. local oscillator for gsm base station v dd v p av dd dv dd adf4116/ adf4117/ adf4118 v p 10k ? vco v cc gnd 18 ? 100pf 100pf 18 ? 18 ? rf out 71516 2 1 6 5 8 f refin 51 ? 100pf 349 100pf cpgnd agnd dgnd rf in a rf in b decoupling capacitors and interface signals have been omitted from the diagram for clarity. fl o cp ce power-down control v dd s in dgnd loop filter adg702 ref in 00392-036 figure 36. local osci llator shutdown circuit
adf4116/adf4117/adf4118 rev. d | page 23 of 28 low-pass filter low-pass filter adf4118 vco190-1960t 18 ? 100pf 18? ref in 100pf rf in a rf in b cp serial digital interface tcxo fox801bh-130 100pf 51 ? 18pf 1k ? 10k ? 6.8nf 18 ? rf out power supply connections and decoupling capacitors are omitted from diagram for clarity. ad9761 txdac refio fs adj modulated digital data qoutb iouta ioutb qouta ibbp qbbp ibbp qbbp ad8346 loin loip vout 100pf 100pf 2k ? 0.1f 100pf 680pf 00392-037 figure 37. direct conversion transmitter solution
adf4116/adf4117/adf4118 rev. d | page 24 of 28 interfacing the adf411x family has a simple spi?-compatible serial inter- face for writing to the device. clk, data, and le control the data transfer. when le (latch enable) goes high, the 24 bits that are clocked into the input register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 s. this is more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 38 shows the interface between the adf411x family and the aduc812 microconverter?. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf411x family needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. sclock mosi i/o ports aduc812 clk data le ce muxout (lock detect) adf4116/ adf4117/ adf4118 00392-038 figure 38. aduc812 to adf411x family interface on first applying power to the adf411x family, it requires three writes (one each to the r counter latch, the n counter latch, and the initialization latch) for the output to become active. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. adsp-21xx interface figure 39 shows the interface between the adf411x family and the adsp-21xx digital signal processor. the adf411x family needs a 21-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. sclk dt i/o flags adsp-21xx clk data le ce muxout (lock detect) adf4116/ adf4117/ adf4118 tfs 00392-039 figure 39. adsp-21xx to adf411x family interface set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 21-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer.
adf4116/adf4117/adf4118 rev. d | page 25 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab figure 40. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option adf4116bru ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4116bru-reel ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4116bru-reel7 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4116bruz 1 ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4116bruz-reel 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4116bruz-reel7 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bru ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bru-reel ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bru-reel7 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bruz 1 ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bruz-rl 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4117bruz-rl7 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4118bru ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4118bru-reel ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4118bru-reel7 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4118bruz 1 ? 40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 ADF4118BRUZ-RL 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 ADF4118BRUZ-RL7 1 ?40c to +85c 16-lead thin shrink small outline package (tssop) ru-16 adf4118yruz 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adf4118yruz-rl 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adf4118yruz-rl7 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 eval-adf4118ebz1 1 evaluation board eval-adf411xebz1 1 evaluation board 1 z = rohs compliant part.
adf4116/adf4117/adf4118 rev. d | page 26 of 28 notes
adf4116/adf4117/adf4118 rev. d | page 27 of 28 notes
adf4116/adf4117/adf4118 rev. d | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2000C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00392-0-4/07(d)

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